PATA ATA 1 0 0 ( 1 P o r t o n ly )
P C I B u s 3 2 b it 3 3 /6 6 M H z
M o d u le Ty p e In d ic a tio n Ty p e [0 :2 ]
C o n n e c to r R o w s C & D
C o n n e c to r R o w s A & B
P C I E x p r e s s L a n e s 0 -5
E x p r e s s C a rd 0 -1
L P C B u s
I² C B u s
S M B u s
A C ’9 7 S D O U T, S D IN (0 :2 ) / H D A
U S B 2 .0 P o r ts 0 - 7
S A TA 0-3
L A N P o r t
+ 1 2 V, V B AT, + 5 V S ta n d b y, G N D
C O M E xp re s s M o d u le
Ty p e 2
LVDS (A&B, dedicated I²C)
GPI[0:3] GPO[0:3]
W atchdog Timeout
Speaker Out
External BIOS ROM Support / SPI
System Reset
Carrier Board Reset
Suspend Control
PCI Express W ake Up Signal
General Purpose W ake Up Signal
Power Good
P C I E x p re s s G r a p h ic s x 1 6
PCI Express Lanes 16-31
OR
SDVO (dedicated I²C)
x16
VGA (dedicated DDC)
Note:
This diagram shows feature sets
available on these connectors.
For pin assignments and actual
positions on the connectors, refer
to the COM.0 R2.1 document.
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