Kontron COMe Starterkit Eval T2 Manual de usuario Pagina 115
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COM Express Interfaces
2.16.2.4. SuperIO
Figure 44: LPC Super I/O Example
PICMG
®
COM Express
®
Carrier Board Design Guide Rev. 2.0 / December 6, 2013
115/218
SUPER I/O
Note: place series resistor near CEX connector
or use buffer for more than 2 LPC load
Note: Internal PD
SIO BOOT STRAPS
RTS0# => Default SIO Addr (2Eh) = 0, Alt SIO Addr (4Eh) = 1
DTR0# => Disable SPI = 0, Enable SPI = 1
TX0 => Disable Keyboard controller (KBC) = 0, Enable KBC = 1
TX1 => CPUFAN1 initial sped 100% = 0, CPUFAN1 initial sped 50% = 1
FAN_SET => CPUFAN0 initial sped 100% = 0, CPUFAN0 initial sped 50% = 1
EN_ACPI => Disable ACPI function = 0, Enable ACPI function = 0
SIO_WDT# => VID transition voltage TTL = 0, VID transition voltage GTL = 1
i
Signals KBD_A20GATE AND KBD_RST#
can be unconnected for completely legacy free system
SIO_SYS_RESET#
SIO_SUS_S5#
SIO_SUS_S3#
LPC_AD0
LPC_AD2
LPC_AD1
LPC_AD3
SIO_ATXPGD
TX0
CLK_48MHz
RTS0#
DTR0#
TX1
LPT_PD0
LPT_PD1
LPT_PD2
LPT_PD3
LPT_PD4
LPT_PD5
LPT_PD6
LPT_PD7
IO_RST#
V_BAT
VCC_3V3_STB
V_BAT
VCC_3V3_STB
VCC_3V3VCC_3V3
VCC_3V3_SBY
VCC_3V3
VCC_3V3
VCC_3V3
CEX
LPC_SERIRQ
CEX
LPC_FRAME#
MCLK
KCLK
MDAT
KDAT
LPT_SLCT
LPT_PE
LPT_BUSY
LPT_ACK#
LPT_SLIN#
LPT_INIT#
LPT_STB#
LPT_ERR#
LPT_AFD#
CEX
SYS_RESET#
CEX
LPC_DRQ0#
CEX
SUS_S3#
CEX
SUS_S5#
CEX
PWR_OK
CEX
LPC_AD[0:3]
CEX
PWR_OK
TX0
RTS0#
DTR0#
CTS0#
DSR0#
RX0
DCD0#
RI0#
TX1
DTR1#
RTS1#
CTS1#
DSR1#
RX1
DCD1#
RI1#
CEX
PCI_PME#
LPT_PD[0:7]
CEX
CB_RESET#
CEX
LPC_CLK
CEX
KBD_A20GATE
CEX
KBD_RST#
R208 4k7
R191
0R
R200
0R
Y4
48MHz / 50ppm
OE
1
GND
2
OUT
3
VCC
4
R223 4k7
R443
2M
C237
1u
R229 4k7
R212 4k7
R363
10k
DNI
FB47
120R@100MHz
R226 4k7
R224 4k7
U30
74125
OE#
1
A
2
GND
3
Y
4
VCC
5
C243
100n
C246
100n
R222 4k7
R205 33R
R216 4k7
R219 4k7
FB57 120R / 0.2A
R209 4k7
R214 4k7
R228 4k7
R225 4k7
R193
0R 5%
R448
R221 4k7
R231 4k7
R227 4k7
R194
R451
1k
R204
10k
C247
22u
C238
10n
R207 22R
R211 4k7
R445
R447
R444
1k
R446
C242
100n
C245
100n
R218 4k7
R217 4k7
R230 4k7
C244
22u
R215 4k7
R213 4k7
R220 4k7
R210 4k7
W83627DHG
PQFP 128
LPC I / F
HARDWARE MONI TOR I / F
PECI I / F
ACPI
KEYBOARD / MOUSE FLOOPY
PARALLEL PORT SERI AL PORT B SERI AL PORT A
U28
W83627DHG-P
GND1
20
LAD3
24
LAD2
25
GND2
55
LAD1
26
LAD0
27
LFRAME#
29
LDRQ#
22
SERIRQ
23
PME#
86
LRESET#
30
IOCLK
18
PCICLK
21
RIA#/GP60
57
DCDA#/GP61
56
SOUTA/GP62/PENKBC
54
SINA/GP63
53
DTRA#/GP64/PENROM
52
RTSA#/GP65/HEFRAS
51
DSRA#/GP66
50
CTSA#/GP67
49
RIB#/GP40
85
DCDB#/GP41
84
SOUTB/GP42/IRTX/FAN_SET2
83
SINB/GP43/IRRX
82
DTRB#/GP44
81
RTSB#/GP45
80
DSRB#/GP46
79
CTSB#/GP47
78
PD0/INDEX2#
42
PD1/TRAK02#
41
PD2/WP2#
40
PD3/RDATA2#
39
PD4/DSKCHG2#
38
PD5
37
PD6/MOA2#
36
PD7/DSA2#
35
SLCT/WE2#
31
PE/WD2#
32
BUSY/MOB2#
33
ACK#/DSB2#
34
SLIN#/STEP2#
43
INIT#/DIR2#
44
ERR#/HEAD2#
45
AFD#/DRVDEN02
46
STB#
47
DRVDEN0
1
DSKCHG#
17
HEAD#
16
RDATA#
15
WP#
14
TRAK0#
13
WE#
11
WD#
10
STEP#
9
DIR#
8
DSA#
6
MOA#
4
INDEX#
3
KDAT/GP26
63
KBRST#
60
GA20M
59
KCLK/GP27
62
MDAT/GP24
66
MCLK/GP25
65
VBAT
74
PSIN#/GP56
68
PSOUT#/GP57
67
VID0
128
VID1
127
VID2
126
VID3
125
VID4
124
CASEOPEN#
76
SMI#/OVT#
5
VREF
101
AUXTIN
102
CPUVCORE
100
3VCC_1
12
3VCC_3
48
3VCC_2
28
AVCC
95
AGND
105
3VSB
61
RSTOUT1#
93
RSTOUT0#
94
SUSB#/GP52
73
PSON#/GP53
72
RSMRST#/GP51
75
VID5
123
VID6
122
VID7
121
VIN0
99
VIN1
98
VIN2
97
VIN3
96
CPUTIN
103
SYSTIN
104
SI/AUXFANIN1
58
AUXFANOUT
7
AUXFANIN0
111
CPUFANIN0
112
CPUFANOUT0
115
GP21/CPUFANIN1
119
GP20/CPUFANOUT1
120
SYSFANIN
113
SYSFANOUT
116
FAN_SET/PLED
117
BEEP/SO
118
PECI_REQ#
110
PECI
108
Vtt
107
PECISB
106
SST
114
NC1
109
PWROK/GP54
71
RSTOUT2#/GP32/SCL
90
RSTOUT3#/GP33/SDA
89
RSTOUT4#/GP34
88
SUSC#/GP37
64
FPTRST#/GP36
69
VSBGATE#/GP31
91
ATXPGD/GP35
87
EN_ACPI/GP55/SUSLED
70
PWROK2/GP30
92
SCK/GP23
2
SCE#/GP22
19
WDTO#/GP50/EN_GTL
77
C241
100n
R291
R292
0R
0R
- COM Express® 1
- Carrier Design Guide 1
- Contents 3
- 1. Preface 8
- 1.6. Name and logo usage 9
- 1.7. Intellectual property 10
- Term Description 11
- 1.10. Schematic Conventions 15
- 2. COM Express Interfaces 16
- COM Expre ss Module 17
- Type 10 17
- Table 4: Pin-out Comparison 20
- , the PCI 30
- 2.3.5. Schematic Examples 34
- Signal Pin Description I/O 45
- Figure 15: ExpressCard Size 45
- 2.4.1. Signal Definitions 48
- 2.4.2. PEG Configuration 49
- 2.4.3. Reference Schematics 52
- DisplayPort is supported 55
- DisplayPort Example 56
- Figure 21: HDMI Example 57
- Figure 22: DVI Example 59
- SDVO Port Configuration 61
- Supported SDVO Devices 62
- DVI_SDAROM 63
- DVI_SCLROM 63
- SDVO I2C Bus Address 63
- Write = 0111 0000 (70h) 63
- Read = 0111 0001 (71h) 63
- 2.6.1. Signal Definitions 66
- Earliest asserted 1ms after 68
- 3.3V, 5V and 12V are stable 68
- 2.7. LAN 70
- 2.7.2. Reference Schematics 73
- 2.8. USB Ports 76
- 2.8.2. Reference Schematics 77
- 2.9. USB 3.0 81
- 2.9.1.3. USB 3.0 connector 83
- 2.9.2. Reference Schematics 84
- 2.10. SATA 87
- Pins Signal Description 88
- SATA Port 89
- 2.11. LVDS 91
- Term Definition 94
- 2.11.2. Reference Schematics 97
- 2.12.1. Signal Definitions 99
- 2.12.2. Reference Schematics 100
- 2.13. VGA 101
- COM Express Interfaces 102
- 2.14. TV-Out 104
- COM Express Module 106
- AUDIO POWER 107
- AUDIO CODEC - ALC888 107
- ANALOG I/O CONNECTOR 107
- 2.15.1.2. AC'97 108
- Figure 41: Audio Amplifier 109
- 2.16.1. Signal Definition 111
- SUPER I/O 115
- COM1/COM2 116
- 2.17.1. Signal Definition 118
- 2.18.1. Signal Definitions 121
- 2.18.2. Reference Schematics 121
- 2.19.1. Signal Definitions 123
- 2.20.1. Signal Definitions 125
- C O M 1 C O M 2 126
- 2.21. CAN Interface 127
- 2.21.2. Reference Schematics 128
- 2.22. Miscellaneous Signals 129
- POWER ATX 133
- POWER AT 133
- Type 2 Detection 133
- 2.22.5. Watchdog Timer 137
- G P IO C o n n e c t o r 141
- 2.22.8. Fan Connector 142
- 2.22.9. Thermal Interface 143
- 2.23. PCI Bus 147
- 2.23.2. Reference Schematics 148
- 2.24.1. Signal Definitions 153
- 3. Power and Reset 156
- 3.2.1. ATX vs AT Supplies 157
- 3.2.2. Power States 157
- Power and Reset 158
- 3.2.5. Power Button 162
- 3.4. Reference Schematics 164
- Table 55: ATX Signal Names 166
- ATX Signal Name Description 166
- 3.5. Routing Considerations 167
- 3.5.3. VCC5_SBY Routing 168
- 4. BIOS Considerations 170
- Type Height Partnumber Note 171
- COM Express Module Connectors 172
- GND Plane 173
- Power Plane 173
- COM Express 175
- Table 60: Trace Parameters 176
- Symbol Definition 176
- Carrier Board 178
- Parameter Trace Routing 183
- Extended 194
- 7.2. Heatspreader 195
- (Ø2.7mm bore hole) 196
- (M2.5 thread) 196
- (Ø2.7 bore hole) 197
- Mechanical Considerations 198
- 8.3. Useful books 202
- 9.1. TV-Out 203
- 9.1.5. Signal Termination 206
- 9.1.6. Video Filter 206
- 9.1.7. ESD Protection 206
- 9.2. LPC Firmware Hub 207
- Appendix C: List of Tables 213
- Appendix D: List of Figures 215
- Table 79: Revision History 217
- Revision Date Author Changes 217
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