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COMe-P2020 User Guide
61
Table 3-45: 0x306: Default eTSEC2 SGMII Mode Configuration Register
ACTION D7 D6 D5 D4 D3 D2 D1 D0
READ NU NU NU NU NU NU NU cfg_sgmii2
WRITENUNUNUNUNUNUNU NU
POWER UP1111111 1
BITFIELD DESCRIPTION
[D0] 0 eTSEC2 Ethernet interface operates in SGMII mode and uses SGMII SerDes
lane 2 pins.
1 eTSEC2 Ethernet interface operates in standard parallel interface mode and
uses the TSEC2_* pins.
Table 3-46: 0x307: Default eTSEC3 SGMII Mode Configuration Register
ACTION D7 D6 D5 D4 D3 D2 D1 D0
READ NU NU NU NU NU NU NU cfg_sgmii3
WRITENUNUNUNUNUNUNU NU
POWER UP1111111 1
BITFIELD DESCRIPTION
[D0] 0 eTSEC3 Ethernet interface operates in SGMII mode and
uses SGMII SerDes lane 3 pins.
1 eTSEC3 Ethernet interface operates in standard parallel
interface mode and uses the TSEC3_* pins.
Table 3-47: 0x308: Default eTSEC1 Width Configuration Register
ACTION D7 D6 D5 D4 D3 D2 D1 D0
READ NU NU NU NU NU NU NU cfg_tsec_reduce
WRITENUNUNUNUNUNUNU NU
POWER UP1111111 1
BITFIELD DESCRIPTION
[D0] 0 eTSEC1 and eTSEC2 Ethernet interfaces operate in reduced pin mode
(either RTBI, RGMII, or RMII mode).
1 eTSEC1 and eTSEC2 Ethernet interfaces operate in their standard width TBI,
GMII, or MII mode.
N O T I C E
Equivalent CPU strapping is hard coded in CPLD depends on board variant, read value is always 0xFE.
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