Kontron COMe-bHL6 Manual de usuario Pagina 68
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COMe-bHL6 / Pinout List
A63 GPI1 General Purpose Input 1 I-3.3 PU 10k 3.3V (S0) -
A64 PCIE_TX1+ PCI Express Lane 1 Transmit + DP-O - -
A65 PCIE_TX1- PCI Express Lane 1 Transmit - DP-O - -
A66 GND Power Ground PWR GND - -
A67 GPI2 General Purpose Input 2 I-3.3 PU 10k 3.3V (S0) -
A68 PCIE_TX0+ PCI Express Lane 0 Transmit + DP-O - -
A69 PCIE_TX0- PCI Express Lane 0 Transmit - DP-O - -
A70 GND Power Ground PWR GND - -
A71 LVDS_A0+ LVDS Channel A Data0 + DP-O - -
A72 LVDS_A0- LVDS Channel A Data0 - DP-O - -
A73 LVDS_A1+ LVDS Channel A Data1 + DP-O - configuration as eDP_TX1+ in customised article version
possible
A74 LVDS_A1- LVDS Channel A Data1 - DP-O - configuration as eDP_TX1- in customised article version
possible
A75 LVDS_A2+ LVDS Channel A Data2 + DP-O - configuration as eDP_TX0+ in customised article version
possible
A76 LVDS_A2- LVDS Channel A Data2 - DP-O - configuration as eDP_TX0- in customised article version
possible
A77 LVDS_VDD_EN LVDS Panel Power Control O-3.3 PD 100k configuration as eDP_VDD_EN in customised article
version possible
A78 LVDS_A3+ LVDS Channel A Data3 + DP-O - -
A79 LVDS_A3- LVDS Channel A Data3 - DP-O - -
A80 GND Power Ground PWR GND - -
A81 LVDS_A_CK+ LVDS Channel A Clock + DP-O - -
A82 LVDS_A_CK- LVDS Channel A Clock - DP-O - -
A83 LVDS_I2C_CK LVDS Data Channel Clock I/O-3.3 PU 2k21 3.3V (S0) configuration as eDP_AUX+ in customised article version
possible
A84 LVDS_I2C_DAT LVDS Data Channel Data I/O-3.3 PU 2k21 3.3V (S0) configuration as eDP_AUX- in customised article version
possible
A85 GPI3 General Purpose Input 3 I-3.3 PU 10k 3.3V (S0) -
A86 RSVD Reserved for future use nc - -
A87 RSVD Reserved for future use nc - configuration as eDP_HPD in customised article version
possible
A88 PCIE_CLK_REF+ Reference PCI Express Clock + DP-O - -
A89 PCIE_CLK_REF- Reference PCI Express Clock - DP-O - -
A90 GND Power Ground PWR GND - -
A91 SPI_POWER 3.3V Power Output Pin for external SPI flash O-3.3 - might be powered during suspend
A92 SPI_MISO SPI Master IN Slave OUT I-3.3 PU 20k in PCH (SPI) resistor value can range from 15kOhm to 40kOhm and
might be powered during suspend
A93 GPO0 General Purpose Output 0 O-3.3 PD 10k -
A94 SPI_CLK SPI Clock O-3.3 - -
A95 SPI_MOSI SPI Master Out Slave In O-3.3 PD 20k in PCH resistor value can range from 15kOhm to 40kOhm
A96 TPM_PP TPM Physical Presence I-3.3 PD 100k -
A97 TYPE10# No Connect for type 6 modules nc - -
A98 SER0_TX Serial Port 0 TXD O-3.3 - 20V protection circuit implemented on module, PD on
carrier board needed for proper operation
A99 SER0_RX Serial Port 0 RXD I-5T PU 47k 3.3V (S0) 20V protection circuit implemented on module
A100 GND Power Ground PWR GND - -
A101 SER1_TX Serial Port 1 TXD O-3.3 - 20V protection circuit implemented on module, PD on
carrier board needed for proper operation
A102 SER1_RX Serial Port 1 RXD I-5T PU 47k 3.3V (S0) 20V protection circuit implemented on module
A103 LID# LID Switch Input I-3.3 PU 47k 3.3V (S5) 20V protection circuit implemented on module
A104 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A105 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A106 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A107 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A108 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A109 VCC_12V Main Input Voltage (8.5-20V) PWR 8.5-20V - -
A110 GND Power Ground PWR GND - -
68
- COMe-bHL6 1
- » Table of Contents « 3
- 1 User Information 6
- 1.5 Warranty 7
- 1.6 Technical Support 7
- 2 Introduction 8
- COMe-bHL6 / Introduction 9
- 2.5 COM Express® Benefits 10
- 3 Product Specification 11
- 3.2 Functional Specification 12
- CPU Features 14
- PCH comparison 16
- Graphics Core 17
- PEG Configuration 18
- Connectivity 19
- Misc Interfaces and Features 19
- Kontron Features 20
- Additional features 20
- Power Features 20
- 3.3 Block Diagram 21
- 3.4 Accessories 22
- 3.5 Electrical Specification 23
- 3.5.5 ATX Mode 24
- 3.5.6 Single Supply Mode 24
- 3.6 Power Control 25
- 3.7.2 Humidity 26
- WEEE Directive 27
- Conformal Coating 27
- Shock & Vibration 28
- 3.9 MTBF 29
- 3.10 Mechanical Specification 30
- 3.11 Module Dimensions 31
- 3.13 Onboard Connectors 33
- 4 Features and Interfaces 35
- 4.2 Rapid Shutdown 36
- 4.5 SPI boot 39
- Using an external SPI flash 40
- 4.6 M.A.R.S 41
- 4.7 UART 42
- 4.8 Fast I2C 43
- Time-out events 44
- WDT Signal 44
- 4.11 Speedstep Technology 47
- 4.12 C-States 48
- 4.13 Hyper Threading 49
- 4.15 VID-x 51
- 4.17 Display Configuration 53
- 3 independent Display Support 54
- DDI Design Consideration 55
- DVI-I Design Topology 55
- Requirements 56
- Setup a Multi-monitor system 56
- 4.19 Intel® Wireless Display 57
- 4.20 Intel® vPro™ technology 59
- 5 System Resources 61
- 5.2 Memory Area 62
- 5.3 I/O Address Map 62
- 5.5 Internal I2C Bus 63
- 5.6 External I2C Bus 63
- 6 Connectors 65
- 7 Pinout List 66
- 7.2 Connector X1A Row A 67
- COMe-bHL6 / Pinout List 68
- 7.3 Connector X1A Row B 69
- 7.4 Connector X1B Row C 71
- 7.5 Connector X1B Row D 73
- 8 BIOS Operation 75
- 8.5 BIOS Setup 76
- System Information 78
- Boot Features 79
- Network Stack 81
- Platform Information 82
- 8.5.2 Advanced 83
- Silicon Information 84
- Processor Configuration 85
- Processor Power Management 86
- Miscellaneous 88
- I2C Speed 89
- Watchdog 90
- Generic LPC Decode Ranges 91
- H/W Monitor 92
- HDD Configuration 94
- Memory Configuration 96
- Graphics Configuration 99
- COMe-bHL6 / BIOS Operation 100
- IGD Configuration 101
- PEG Port Configuration 103
- South Bridge Configuration 105
- SB PCI Express Config 106
- SB USB Config 108
- SB Azalia Config 109
- Network Configuration 110
- CPLD Configuration 111
- LPC SIO Configuration 112
- ME Configuration (default) 115
- Thermal Configuration 117
- CPU Thermal Configuration 118
- Passive Cooling 120
- ICC Configuration 121
- Intel® Rapid Start Technology 123
- 8.5.3 Security 125
- Security 126
- 8.5.4 Boot 127
- 8.5.5 Exit 128
- Corporate Offices 129
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