
KT690 Family
Chipset Menu 8.7
Main Advanced PCIPnP Boot Security Chipset Exit
Advanced Chipset Settings
Bridge features.
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
>
>
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Warning: Setting wrong values in below sections
may cause system to malfunction.
North Bridge Configuration
South Bridge Configuration
AMD 690G Configuration
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
8.7.1 Advanced Chipset Settings – North Bridge Chipset Configuration
North Bridge Adapter Priority Configuration
power down mode by
deasserting the clock
enable signal when
DIMMs are not in use.
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Power Down Control [Auto]
Memory CLK :400 MHz
CAS Latency(Tcl) :5.0
RAS/CAS Delay(Trcd) :5 CLK
Min Active RAS(Tras) :18 CLK
Row Precharge Time(Trp):5 CLK
RAS/RAS Delay(Trrd) :3 CLK
Row Cycle (Trc) :24 CLK
Asynchronous Latency :6 ns
V02.59+ (C)Copyright 1985-2005, American Megatrends, Inc.
Disabled
Allow DIMMs to enter power down mode by
deasserting the clock enable signal when DIMMs are
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