
KT690 Family
4.4.3 LVDS Flat Panel Connector (LVDS)
Note 1: The KT690 board support dual channel, 24bit OpenLDI/ SPWG panels on the LVDS interface
Signal Description – LVDS Flat Panel Connector:
Signal Description
LVDS A0..A3 LVDS A Channel data
LVDS ACLK LVDS A Channel clock
LVDS B0..B3 LVDS B Channel data
LVDS BCLK LVDS B Channel clock
BKLTCTL Backlight control (1), PWM signal to implement voltage in the range 0-3.3V
BKLTEN# Backlight Enable signal (active low) (2)
VDD ENABLE Output Display Enable.
LCDVCC VCC supply to the flat panel. This supply includes power-on/off sequencing.
The flat panel supply may be either 5V DC or 3.3V DC depending on the CMOS
configuration. Maximum load is 1A at both voltages.
DDC CLK DDC Channel Clock
DDC DATA DDC Channel Data
Note 1) Windows API will be available to operate the BKLTCTL signal. Some Inverters has a limited voltage
range 0- 2.5V for this signal: If voltage is > 2.5V the Inverter might latch up. Some Inverters
generates noise to the BKLTCTL signal resulting in making the lvds transmision fail (corrupted
picture on the display). By adding 1K Ohm resistor in series with this signal and mounted in the
Inverter end of the cable kit the noise is limited and picture is stabil.
Note 2) If the Backlight Enable is required to be active high then make the BIOS Chipset setting: Backlight
Signal Inversion = Enabled.
Comentarios a estos manuales