
Introduction AM4150
Page 1 - 6 ID 1051-5040, Rev. 2.0
1.4.1 Functional Block Diagram
Figure 1-1: AM4150 Functional Block Diagram
2 banks of DDR3 SDRAM soldered
up to 8 GB w ECC
Front Panel
FPGA
Board Control
MMC
Temp.
Sense
AMC Connector
Port No.
0,1
IPMB-L
Serial
Fat Pipe Region
Serial
COP/
JTAG
EEP
2 Banks of Soldered DDR3 SDRAM
with ECC
Dual-Core
Freescale™
Power Architecture®
QorIQ™ P5020
64-bit
up to 2.2 GHz
DDR3
Common Options Region
GbE
RJ-45
with int.
Mag.
Flash
RTC
RJ-45
Serial
SGMII
NAND
Flash
eLBC
System
EEP
SPI
DUART
DUART
COP
15
Local Bus
FRU
8-11
Extended Options Region
I²C
SDHC
MicroSD Card
Socket
Debug Debug
14
GbE A, GbE B
4-7
2x RGMII
Dual
Gigabit
Ethernet
PHY
User
EEP
I²C
SATA A
SATA B
SATA Flash
Module
sRIO x4 or PCIe x4
2
3
SATA
SATA
MUX
sRIO x4 or PCIe x4
or max. 3x GbE SerDes
RJ-45
with int.
Mag.
GbE
MDI to Front
2x SerDes
SerDes
SerDes
SerDes
RCW config.
SRDS PRTCL
SPD
EEP
4x GPIO (on request)
16 4x GPIO (on request)
RS-232
SPI
Flash
for OS
SPI Boot
Flashes
(standard/
recovery)
dTSEC
dTSEC
SerDes
SerDes
SerDes
SerDes
SerDes
4x SerDes
(Opt.)
Gigabit
Ethernet
PHY
Health LED
Hot Swap LED
ut
se
-Specific LEDs
Front Panel
LEDs
Hot Swap
Handle Switch
MDI
up to 1300 MHz
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